The present invention relates in general to a semiconductor device, and more particularly to an improved clock-synchronizing semiconductor memory device operable in output in synchronizing with clock signals.
FIG. 1 is a block diagram illustrative of a conventional clock-synchronizing semiconductor memory device. A structure of the conventional clock-synchronizing semiconductor memory device will be described with reference to FIG. 1.
The conventional clock-synchronizing semiconductor memory device has an address register 1 for receiving an address input and outputting address data in synchronizing with an externally inputted clock signal "CLK". The address register 1 sends the input value to the output side upon rise-edge of the clock signal "CLK" for subsequent holding the value until the next rise-edge of the clock signal "CLK". Further, an address decoder 2 is provided which is connected to the address register 1 for receiving the address data from the address register 1. A memory cell array is also provided which is connected to the address decoder 2 for receiving the address data from the address decoder 2. An input register 6 is also provided which receives data externally inputted. The input register 6 also receives the clock signal "CLK" so that the input register 6 is operable in synchronizing with the clock signal "CLK". The input register 6 sends the input value to the output side upon rise-edge of the clock signal "CLK" for subsequent holding the value until the next rise-edge of the clock signal "CLK". The input register 6 is connected to the memory cell array 3 so as to transmit data to the memory cell array 3, whereby the data are stored in the memory cell array 3 at a designated address from the address decoder. An output register 4 is further provided which is connected to the memory cell array 3 for fetching the data from the memory cell array 3. The output register 4 receives the clock signal "CLK" so that the output register 4 is operable in synchronizing with the clock signal "CLK". The output register 4 sends the input value to the output side upon rise-edge of the clock signal "CLK" for subsequent holding the value until the next rise-edge of the clock signal "CLK". An output buffer 5 is further provided which is connected to the output register 4 for receiving the output data from the output resistor 4. The output buffer 5 is controlled by the following signals and circuits. A register 7 is provided which receives the clock signal "CLK" and a chip select enable signal "CE". A NAND gate 11 is also provided which has two inputs, one of which is connected to an output of the register 7, for receiving the chip select enable signal "CE" and an output signal from the register 7. The register 7 is operable in synchronizing with the clock signal "CLK". The register 7 sends the input value to the output side upon rise-edge of the clock signal "CLK" for subsequent holding the value until the next rise-edge of the clock signal "CLK". A NOR gate 12 is also provided which has two inputs, one of which is connected to an output of the NAND gate 11, for receiving an output signal from the NAND gate 11 and a write enable signal "WE". An output enable register 8 is also provided which has two inputs, one of which is connected to an output of the NOR gate 12, for receiving an output from the NOR gate 12 and also receiving the clock signal CLK. The output enable resistor 8 is operable in synchronizing with the clock signal CLK to output an output "CE2". The output enable register 8 sends the input value to the output side upon rise-edge of the clock signal "CLK" for subsequent holding the value until the next rise-edge of the clock signal "CLK". An invertor 13 is also provided which has an input for receiving an output enable signal "OE-bar" and then outputting the output enable signal "OE". An AND gate 10 is also provided which has two inputs, wherein one input is connected to an output of the output enable register 8 for receiving the output "CE2" from the output enable register 8 and another input is connected to an output of the invertor 13 for receiving the output enable signal "OE" from the invertor 13. The output enable signal "OE" is not synchronizing with the clock signal CLK, whilst the output "CE2" is synchronizing with the clock signal CLK. The AND gate 10 has an output which is connected to the output buffer 5 so that the output buffer 5 is controlled by the output signal from the AND gate 10.
Operations of the above conventional clock-synchronizing semiconductor memory device will be described with reference again to FIG. 1. The output operation of the output buffer 5 is made under the control in accordance with an output control logic signal from the AND gate 10. This output control logic signal is determined by both the value "CE2" transmitted from the output enable register 8 and the output enable signal "OE" from the invertor 13. Namely, the output operation of the output buffer 5 depends upon both the value "CE2" transmitted from the output enable register 8 and the externally inputted output enable signal "OE-bar". A value to be inputted into the output enable register 8 is determined by the write-enable signal "WE" and the chip select enable signal "CE".
In write-state, the write enable signal is in high level, for which reason the output "CE2" of the output enable register 8 becomes low level upon the next rise of the clock cycle of the clock signal CLK, whereby the output buffer 5 enters into the high impedance state. When the write enable signal "WE" is in the low level and the chip select enable signal "CE" is in the high level, then the output enable signal "OE-bar" being in the low level makes the output buffer in the low impedance state, resulting in an output of the value having stored in the output register 4.
If the chip select signal enters into the high level at the same time when the address is inputted into the address register 1, then the data are outputted from the output buffer 5 in the next clock cycle, for which reason the output timing of the data from the output buffer 5 is adjusted by the register 7.
In the meantime, the above conventional semiconductor memory device has the following problems.
In a time duration from a power-ON to an initial rise of the clock cycle of the clock signal "CLK", an output value of the output enable register 8 is indefinite. Namely, in the time duration from the power-ON to the rise of the initial clock cycle of the clock signal "CLK", the output buffer may enter into the low impedance state whereby a short circuit current may be applied between the input terminal of this semiconductor memory device and other semiconductor device.
In order to prevent the short circuit current, it is required that the output enable signal "OE-bar" not synchronizing with the clock signal "CLK" is fixed at the high level upon the power ON to keep the output buffer 5 in the high impedance state. Otherwise, it is required to add an additional circuit which is operated to set the value stored in the output enable register so that the output from the register becomes low level upon power-ON.
FIG. 2 is a circuit diagram illustrative of a circuit configuration of the output enable register 8 of the conventional clock-synchronizing semiconductor memory device shown in FIG. 1. Operations of the output enable register 8 will be described with reference to FIG. 2. If, immediately after the power-ON, a power voltage does not achieve a threshold voltage of a p-channel MOS field effect transistor P4, then a node 41 has a voltage of 0 V, whereby a p-channel MOS field effect transistor P3 becomes conductive to an n-channel MOS field effect transistor N2. A value stored in a register is held, wherein the register comprises a master slave flip flop circuit which comprises a transfer gate and an invertor. After the power voltage becomes beyond the threshold voltage of the p-channel MOS field effect transistor P4, then the p-channel MOS field effect transistor P4 enters into a conductive state, whereby the potential of the node 41 is risen to place the p-channel MOS filed effect transistor P3 and the n-channel MOS field effect transistor N2 into the non-conductive state.
In the above manners, the value from the output enable register 8 can be held at the low level upon the power-ON. However, a transistor is used which has a larger size than that of the invertor constituting the register. For this reason, after the register is commenced to operate by the clock signal "CLK", an operational speed of the register is dropped due to capacitances of the drains of the p-channel MOS field effect transistor P3 and the n-channel MOS field effect transistor N2.
In the above circumstances, it had been required to develop a novel clock-synchronizing semiconductor memory device free from the above problems.